1. Field of Invention
The present invention relates to a semiconductor package structure. More particularly, the present invention relates to a chip package structure and a substrate within the package structure.
2. Description of Related Art
At present, manufacturing technologies for fabricating semiconductor devices are progressing at a tremendous pace. Consequently, the level of integration for integrated circuit (IC) chips has advanced in stages from small-scale integration (SSI) to large-scale integration (LSI) or even ultra-large scale integration (ULSI). No matter what the applications actually are for, these integrated circuits are formed by various fabrication techniques on a silicon wafer. The total number of usable integrated circuits in each wafer depends on the type of fabrication techniques and the gate counts of the each integrated circuit. The wafer is later diced up into dies each having a complete integrated circuit unit. Thereafter, the die is packaged within a plastic body that can be attached to a conventional printed circuit board (PCB).
Due to rapid increase in the level of integration, each integrated circuit has increasingly complicated functional capabilities. Hence, the number of input/output (I/O) leads from a package required for external connection must be increased. To accommodate additional connections, the packaging design must be revised and continuously improved. Earlier quad flat pack (QFP) where the die is attached to a lead frame no longer can meet the pin count of later versions of highly integrated chips. Even the capacity of a later version such as the pin-grid array cannot meet the large pin count demanded by a modem chip. Therefore, a package based on attaching a die on a small piece of printed circuit board or substrate known as a ball grid array (BGA) package has been developed. Since the introduction of BGA packages for housing high pin count integrated circuit chips, it has become the dominant packaging technique.
FIG. 1 is a diagram showing the substrate of a conventional north bridge chip package. In FIG. 1, only the surface of the substrate 100 for attaching a die is shown. Furthermore, to simplify the identification of components, wire-bonding pads for connection to contact pads on the die and wiring for distributing signals from the I/O leads of the die are omitted.
In general, the north bridge chip is connected to a central processing unit (CPU), an accelerated graphic port (AGP), a system memory and a south bridge chip. Hence, the north bridge chip must include a central processing control unit, an accelerated graphic port control unit, a memory control unit and a south bridge chip control unit (not shown). Since the input/output (I/O) ports of the north bridge chip have to transmit signals to various I/O ports of connected devices, the substrate 100 within the north bridge chip must also supply power to the devices.
As shown in FIG. 1, the north bridge chip has a power layout that includes a ground region 110 and a plurality of power source regions 120, 130, 140, 150 and 160. The ground region 110 is used for attaching a die and ground leads of the die. The power source 120 provides a supply power (Vcc1) to the input/output (I/O) section of the accelerated graphic port control unit of the die. In general, the power source 120 provides 1.5V. The power source 130 provides a supply power (Vcc2) to the input/output (I/O) section of the south bridge chip control unit. In general, the power source 130 provides 1.5V. The power source 140 provides a to supply power (Vcc3) to the input/output (I/O) section of the memory control unit. In general, the power source 140 provides 2.5V. The power source 150 provides a supply power (Vtt) to the input/output (I/O) section of the central processing control unit. In general, the power source 150 provides 1.5V. The power source 160 provides a supply power (Vcore) to the core section of various units within the die. In general, the power source 160 provides 2.5V.
To transmit signals from a unit within the north bridge chip to an external device, the voltage between the external device and the I/O ports of unit need to be transformed. FIG. 2 is the diagram of a conventional signal driving circuit. In FIG. 2, the input signal Sin passes through a core driver 210 and an I/O driver 220 as an output signal Sout. The voltage Vcore powers the core driver 210 while the voltage Vtt powers the I/O driver 220. As seen from FIGS. 1 and 2, the substrate of a conventional north bridge chip package structure has no provision for isolating the power at the core section of various control units. Hence, the voltage at the core section of the power source 160 may fluctuate when subjected to a high frequency signal. Fluctuation in the power source may directly interfere with the operations of other units within the north bridge and ultimately lead to circuit instability.